ASIC Design of High-Speed Low-Power HDLC Controller
摘要
Combined with the engineering requirement, a high-speed low-power ASIC design of HDLC controllerbased on RS-485 bus is given in this paper.On principle of Top-Down design, this ASIC design usesmulti-techniques to reduce its die area and dynamic power,and overcomes some problems appeared frequently inapplication systems of the RS-485 circuits formed by the Standard Interface Chips. This design also improves thesystem reliability and reduces the system area.
引用本文（GB/T 7714）
陈禾, H.Y. Liu C.J. Qiu. ASIC Design of High-Speed Low-Power HDLC Controller[J]. 北京理工大学学报：英文版, 2003.
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