A Design of Vectored Interrupt Controller Supporting Multiple FIQ
摘要
To reduce the time overhead of assigning multiple Fast Interrupt Request(FIQ),a vectored interrupt controller for FIQ interrupt source identification and priority arbitration is designed.It is described by Verilog-HDL.Modelsim simulation and FPGA verification are also passed.Synthesis is completed with SMIC 0.13 μm CMOS technology,as well as place and route.Simulation and verification results show that the area is 0.107 mm2,the average power is 3.56 mW and the frequency is 80 MHz.This design can meet the real time demand of the chip in mobile communication RF SoC.
引用本文（GB/T 7714）
ZHU Xiding,ZHANG Tao,YU Ziqi,HU Zhichuan. A Design of Vectored Interrupt Controller Supporting Multiple FIQ[J]. DOAJ (DOAJ: Directory of Open Access Journals), 2017.
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