Design and Verification of Efficient PLB2AXI Bus Bridge
摘要
In order to realize the protocol conversion and efficient communication between different IP cores of the System on Chip(SoC),an efficient PLB2AXI bus bridge design scheme is proposed.By taking advantage of the bandwidth of PLB bus and AXI bus,the address,data and control signals in PLB bus protocol are converted into corresponding signals in AXI bus protocol by introducing the mechanism of pipeline transmission and read-write overlapping transmission,so as to implement the communication between two bus protocols.The functions of PLB2AXI bus bridge is verified at the module level and FPGA system level.The results show that the master cable-bridge of this scheme can converse protocol correctly,and time consuming is only 54.41% of that of the traditional master cable-bridge,so it has a higher conversion and transmission efficiency.