A High Performance Full Duplex DMA Design for Cryptographic SoC
摘要
In data-intensive applications such as cryptographic SoC,data transmission speed has gradually become a bottleneck restricting cipher processing performance.To address the problem,this paper proposes an optimized high performance DMA design method for cryptographic SoC based on the characteristics of stream processing in cryptographic SoC.First,a dedicated channel for DMA transfer of a specific module is opened,and data is read/written in parallel to improve the utilization rate of bus bandwidth in DMA transmission of a specific module.Second,a special work mode is added for autonomous control of repeated task transmission,so as to improve the utilization rate of transmission bandwidth.On this basis,dynamic adjustment technology based on multi-channel priority optimization is used to achieve more efficient adaptive transmission under multiple tasks.Simulation results show that the highest frequency of the proposed DMA in the 55 nm process is 910 MHz.The average utilization rate of bus and the coprocessor is 91% and 54% respectively.Compared with the general design of DMA,the proposed design increases the performance of ZUC,SNOW,SM3,SM4 and AES algorithms to cryptographic SoC by 216%,222%,123%,69% and 221% respectively.