Design of imaging system of interline area CCD
摘要
A complete imaging system was designed and implemented by using a interline CCD KAI- 1020 as image sensor. Field-Programmable Gate Array (FPGA) was adopted as the core controller of the whole system, which generated driving sequences, controlled the CCD power-up sequence, adjusted the exposure time and realized data cache. After preprocessing, CCD analog video output was transferred via coaxial cable to the dedicated CCD signal processor for correlated double sampling (CDS) and analog- digital conversion, and it finally outputted to FPGA in the form of 10-bit digital signal. CCD digital video signal was drove by differential line driver and then acquired by the image acquisition card in low voltage differential signaling (LVDS) format. The use of integrated CCD signal processor improved the system's signal to noise ratio and enhanced the image quality. Experimental results show that the designed CCD imaging system works normally and stably, the frame rate is 10 frames/s when the pixel readout clock is 10 MHz. The designed CCD imaging system characterizes good performance, high reliability, and short implementation cycle and provides high expansibility.