FPGA-Based Efficient Programmable Polyphase FIR Filter

2005北京理工大学学报：英文版Engineering被引 3

摘要

The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.)

引用本文（GB/T 7714）

Hua Wang. FPGA-Based Efficient Programmable Polyphase FIR Filter[J]. 北京理工大学学报：英文版, 2005.

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