基于混沌的公开可验证FPGA知识产权核水印检测方案
摘要
IP (intellectual property) infringement has been a serious problem to FPGA vendors or IP designer. Watermarking is a novel technique for FPGA IP protection, while existing FPGA watermarking techniques may give away sensitive information during the public verification (e.g. the content or position of watermarks), which enables malicious verifiers or third parties to remove the watermarks and resell the design. Existing zero-knowledge watermarking verification schemes are able to address the sensitive information leakage issue but are vulnerable to embedding attacks, which makes it ineffective in preventing denying infringement of un-trusted buyers (verifiers). This paper presents a new chaotic-based publicly verifiable zero knowledge watermark detection scheme for FPGA IP protection. This scheme is both resilient against the sensitive information leakage issue and removing attacks, thus robust to cheating from provers, verifiers or the third party. In traditional FPGA watermarking techniques, watermarks are embedded in the used Slices, thus the area overhead is proportional to the number of embedded watermarks. In the proposed scheme, watermarks are hidden in the unused LUTs of used Slices, introducing zero area and timing overheads. Chaotic systems are sensitive to initial values and convenient to produce numerous pseudo-random numbers with ultra-low coefficients and perfect statistical property. These advantages match the specific requirements for the random location permutation of the LUTs in the FPGA bit-stream file in the zero knowledge protocol, bringing an ultra-high robustness of LUT location permutation. The timestamp mechanism is also introduced in this paper to resist embedding attacks against denying the infringement from un-trusted IP buyers (verifiers). Experimental results and analysis show that the proposed scheme is significantly better than the latest related literatures in both watermarking overheads and robustness of location permutation.