超低功耗集成电路技术
摘要
Integrated circuit technology follows Moores Law scaling down to the nano-scale, and the power consumption challenges become a bottleneck restricting integrated circuit technology development. The development of microelectronics technology has entered the power constraints era. Power consumption becomes a critical issue of integrated circuit design and manufactory. Reducing power consumption may take the place of improving integration and reducing the size of the device, and becomes the driving force of future integrated circuit technology development. The realization of low-power integrated circuits is systematic engineering. From the device level to circuit level and system level, power optimizations should be taken into account, and a tradeoff between performance and power consumption is needed. As CMOS technology scaling down to nano-scale, the effects of leakage current and parasitics of MOSFET become serious issues. Many traditional low-power technologies become a “stopgap” solution, and are difficult to fundamentally solve the problem of the power constraints encountered in the development of integrated circuits. Moreover, the power constraints have affected the sustainable development of nano-scale integrated circuits. In this paper, based on in-depth analysis of all aspects affecting the power consumption of integrated circuits, the technology, the device structure and design methods for the ultra-low-power integrated circuit application are introduced.