高性能处理器层次化可重用模拟验证环境
摘要
Multi-core and SoC integration have become the trend for high-performance processor development; this has made processor design more complex and chip scale even larger. Flat simulation verification environments consume a large amount of computer resources, which can cause the speed of the simulation to decline sharply, and consequently, it can result in poor simulation efficiency. However, simulation is still the most widely used method for processor verification, and processor simulation environment is crucial to simulation efficiency. Based on the processor architecture and the rules for reuse of verification components, a hierarchical reusable simulation verification environment can significantly solve the problems of large memory consumption, low simulation speed, and low verification efficiency. This method can also shorten the establishing and debugging periods, reduce mistakes in the environment, and make the simulation environment more easily reusable for different processor verifications.