高k 栅MOSFET 栅-源/漏寄生电容的半解析模型
摘要
This paper proposes a two-dimensional boundary value problem for a high-k gate dielectric MOSFET and its sidewall spacer oxide. We have calculated the two-dimensional electrical potential distribution and charge distribution. A model of parasitic capacitance between the gate and the source/drain for a MOSFET has been given. In this paper, we also analyze the relationship between these parasitic capacitances and geometry dimension parameters with a semi-analytical method. The results show that there is a smallest parasitic capacitance by changing the magnitude of gate dielectric constant. The accuracy of the method is tested by comparing the modeled results with CST (computer simulation technology) simulation results. Satisfactory agreement is observed between calculation results of the model and the prediction made by CST.