An improved single-loop sigma-delta modulator for GSM applications
摘要
Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer.This paper presents an improved 4th-order 1 -bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement low-distortion.The modulator was fabricated in a 0.35μm CMOS process,and it achieved 92.8 dB SNDR and 101 dB DR with a signal bandwidth of 100 kHz dissipating 8.6 mW power from a 3.3-V supply.The performance satisfies the requirements of a GSM system.
引用本文（GB/T 7714）
李宏义, 王源, 贾嵩, 等. An improved single-loop sigma-delta modulator for GSM applications[J]. 半导体学报：英文版, 2011.
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